module disp_scan (
    input             CLK,
    input      [31:0] DATA_in,
    output reg [ 7:0] SEG,
    output reg [ 7:0] WORD_SEL
);
  reg [2:0] CNT;
  reg [3:0] DATA;
  always @(CNT) begin
    case (CNT)
      3'd0: begin
        WORD_SEL <= 8'b00000001;
        DATA     <= DATA_in[3:0];
      end
      3'd1: begin
        WORD_SEL <= 8'b00000010;
        DATA     <= DATA_in[7:4];
      end
      3'd2: begin
        WORD_SEL <= 8'b00000100;
        DATA     <= DATA_in[11:8];
      end
      3'd3: begin
        WORD_SEL <= 8'b00001000;
        DATA     <= DATA_in[15:12];
      end
      3'd4: begin
        WORD_SEL <= 8'b00010000;
        DATA     <= DATA_in[19:16];
      end
      3'd5: begin
        WORD_SEL <= 8'b00100000;
        DATA     <= DATA_in[23:20];
      end
      3'd6: begin
        WORD_SEL <= 8'b01000000;
        DATA     <= DATA_in[27:24];
      end
      3'd7: begin
        WORD_SEL <= 8'b10000000;
        DATA     <= DATA_in[31:28];
      end
      default: begin
        WORD_SEL <= 8'b00000000;
        DATA     <= 0;
      end
    endcase
  end

  always @(posedge CLK) begin
    if (CNT == 3'd7) begin
      CNT <= 3'd0;
    end else begin
      CNT <= CNT + 1;
    end
  end

  always @(DATA) begin
    case (DATA)
      4'b0000: SEG <= 8'b11000000;  // C0 0
      4'b0001: SEG <= 8'b11111001;  // F9 1
      4'b0010: SEG <= 8'b10100100;  // A4 2
      4'b0011: SEG <= 8'b10110000;  // B0 3
      4'b0100: SEG <= 8'b10011001;  // 99 4
      4'b0101: SEG <= 8'b10010010;  // 92 5
      4'b0110: SEG <= 8'b10000010;  // 82 6
      4'b0111: SEG <= 8'b11111000;  // F8 7
      4'b1000: SEG <= 8'b10000000;  // 80 8
      4'b1001: SEG <= 8'b10010000;  // 90 9
      4'b1010: SEG <= 8'b10001000;  // 88 A
      4'b1011: SEG <= 8'b10000011;  // 83 B
      4'b1100: SEG <= 8'b11000110;  // C6 C
      4'b1101: SEG <= 8'b10100001;  // D1 D
      4'b1110: SEG <= 8'b10000110;  // 86 E
      4'b1111: SEG <= 8'b10001110;  // 8E F
      default: SEG <= 8'b00000000;
    endcase
  end

endmodule
